View CAT93C46RYI-G3_3753038.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

?2006 by catalyst semiconductor, inc. characteristics subject to change without notice 1 doc. no. 1107, rev. f features high speed operation: 4mhz @ 5v, 2mhz @ 1.8v 1.8v to 5.5v supply voltage range selectable x8 or x16 memory organization sequential read software write protection power-up inadvertent write protection low power cmos technology 1,000,000 program/erase cycles 100 year data retention industrial temperature range rohs-compliant 8-pin pdip, soic, tssop and 8-pad tdfn packages pin configuration description the cat93c46r is a 1-kb cmos serial eeprom device which is organized as either 64 registers of 16 bits or 128 registers of 8 bits, as determined by the state of the org pin. the cat93c46r features sequential read and self-timed internal write with auto- clear. on-chip power-on reset circuitry protects the internal logic against powering up in the wrong state. in contrast to the cat93c46, the cat93c46r features an internal instruction clock counter which provides improved noise immunity for write/erase commands. functional symbol note: when the org pin is connected to v cc , the x16 organization is selected. when it is connected to ground, the x8 pin is selected. if the org pin is left unconnected, then an internal pull-up device will select the x16 organization. cs sk di org do v cc gnd cat93c46r pin functions pin name function cs chip select sk clock input di serial data input do serial data output v cc power supply gnd ground org memory organization nc no connection cat93c46r 1-kb microwire serial eeprom pdip (l) soic (v, x) tssop (y) tdfn (vp2) soic (w) 8 7 6 5 v cc nc org gnd di cs sk do 1 2 3 4 8 7 6 5 org gnd do di cs nc v cc sk 1 2 3 4 for ordering information details, see page 12. * the green & gold seal identifies rohs-compliant packaging, using nipdau pre-plated lead frames.
cat93c46r 2 doc. no. 1107, rev. f ?2006 by catalyst semiconductor, inc. characteristics subject to change without notice d.c. operating characteristics v cc = +1.8v to +5.5v, unless otherwise specified. symbol parameter test conditions min max units i cc1 power supply current f sk = 1mhz 1 ma (write) v cc = 5.0v i cc2 power supply current f sk = 1mhz 500 a (read) v cc = 5.0v i sb1 power supply current cs = 0v 10 a (standby) (x8 mode) org = gnd i sb2 power supply current cs = 0v 10 a (standby) (x16mode) org = float or v cc i li input leakage current v in = 0v to v cc 2 a i lo output leakage current v out = 0v to v cc ,2 a (including org pin) cs = 0v v il1 input low voltage 4.5v v cc < 5.5v -0.1 0.8 v v ih1 input high voltage 4.5v v cc < 5.5v 2 v cc + 1 v v il2 input low voltage 1.8v v cc < 4.5v 0 v cc x 0.2 v v ih2 input high voltage 1.8v v cc < 4.5v v cc x 0.7 v cc +1 v v ol1 output low voltage 4.5v v cc < 5.5v 0.4 v i ol = 2.1ma v oh1 output high voltage 4.5v v cc < 5.5v 2.4 v i oh = -400 a v ol2 output low voltage 1.8v v cc < 4.5v 0.2 v i ol = 1ma v oh2 output high voltage 1.8v v cc < 4.5v v cc - 0.2 v i oh = -100 a absolute maximum ratings (1) storage temperature -65 c to +150 c voltage on any pin with respect to ground (2) -0.5 v to +6.5 v reliability characteristics (3) l o b m y sr e t e m a r a pn i ms t i n u n d n e ) 4 ( e c n a r u d n e0 0 0 , 0 0 0 , 1s e l c y c e s a r e / m a r g o r p t r d n o i t n e t e r a t a d0 0 1s r a e y note: (1) stresses above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions outside of those listed in the operational sectio ns of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and re liability. (2) the dc input voltage on any pin should not be lower than -0.5v or higher than v cc +0.5v. during transitions, the voltage on any pin may undershoot to no less than -1.5v or overshoot to no more than v cc +1.5v, for periods of less than 20 ns. (3) these parameters are tested initially and after a design or process change that affects the parameter according to appropria te aec-q100 and jedec test methods. (4) block mode, v cc = 5v, t a = 25 c.
cat93c46r 3 doc no. 1107, rev. f ?2006 by catalyst semiconductor, inc. characteristics subject to change without notice pin capacitance symbol test conditions max units c out (1) output capacitance (do) v out = 0v 5 pf c in (1) input capacitance (cs, sk, di, org) v in = 0v 5 pf v cc = 1.8v- 5.5v v cc = 4.5v- 5.5v symbol parameter min max min max units t css cs setup time 50 50 ns t csh cs hold time 0 0 ns t dis di setup time 100 50 ns t dih di hold time 100 50 ns t pd1 output delay to 1 0.25 0.1 s t pd0 output delay to 0 0.25 0.1 s t hz (1) output delay to high-z 100 100 ns t ew program/erase pulse width 5 5 ms t csmin minimum cs low time 0.25 0.1 s t skhi minimum sk high time 0.25 0.1 s t sklow minimum sk low time 0.25 0.1 s t sv output delay to status valid 0.25 0.1 s sk max maximum clock frequency dc 2 dc 4 mhz a.c. characteristics (2) note: (1) these parameters are tested initially and after a design or process change that affects the parameter according to appropria te aec-q100 and jedec test methods. (2) test conditions according to ?.c. test conditions?table. (3) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. a.c. test conditions input rise and fall times 50ns input pulse voltages 0.4v to 2.4v 4.5v v cc 5.5v timing reference voltages 0.8v, 2.0v 4.5v v cc 5.5v input pulse voltages 0.2v cc to 0.7v cc 1.8v v cc 4.5v timing reference voltages 0.5v cc 1.8v v cc 4.5v output load current source i olmax /i ohmax ; c l = 100pf power-up timing (1)(3) symbol parameter max units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms
cat93c46r 4 doc. no. 1107, rev. f ?2006 by catalyst semiconductor, inc. characteristics subject to change without notice device operation the cat93c46r is a 1024-bit nonvolatile memory intended for use with industry standard microproces- sors. the cat93c46r can be organized as either registers of 16 bits or 8 bits. when organized as x16, seven 9-bit instructions control the reading, writing and erase operations of the device. when organized as x8, seven 10-bit instructions control the reading, writing and erase operations of the device. the cat93c46r oper- ates on a single power supply and will generate on chip the high voltage required during any write operation. instructions, addresses, and write data are clocked into the di pin on the rising edge of the clock (sk). the do pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. the ready/busy status can be determined after the start of a write operation by selecting the device (cs high) and polling the do pin; do low indicates that the write operation is not completed, while do high indicates that the device is ready for the next instruction. if necessary, the do pin may be placed back into a high impedance state during chip select by shifting a dummy ??into the di pin. the do pin will enter the high impedance state on the rising edge of the clock (sk). placing the do pin into the high impedance state is recommended in applica- tions where the di pin and the do pin are to be tied together to form a common di/o pin. the ready/busy flag can be disabled only in ready state; no change is allowed in busy state. the format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit address (an additional bit when organized x8) and for write operations a 16-bit data field (8-bit for x8 organization). read upon receiving a read command and an address (clocked into the di pin), the do pin of the cat93c46r will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (msb first). the output data bits will toggle on the rising edge of the sk clock and are stable after the specified time delay (t pd0 or t pd1 ). sequential read after the 1st data word has been shifted out and cs remains asserted with the sk clock continuing to toggle, the cat93c46r will automatically increment to the next address and shift out the next data word. as long as cs is continuously asserted and sk continues to toggle, the device will keep incrementing to the next address automatically until it reaches the end of the address space, then loops back to address 0. in the sequential read mode, only the initial data word is preceeded by a dummy zero bit; all subsequent data words will follow without a dummy zero bit. erase/write enable and disable the cat93c46r powers up in the write disable state. any writing after power-up or after an ewds (write disable) instruction must first be preceded by the ewen (write enable) instruction. once the write instruction is enabled, it will remain enabled until power to the device is removed, or the ewds instruction is sent. the ewds instruction can be used to disable all cat93c46r write and erase instructions, and will prevent any accidental writing or clearing of the device. data can be read normally from the device regardless of the write enable/ disable status. instruction set n o i t c u r t s n it i b t r a t se d o c p o s s e r d d aa t a d s t n e m m o c 8 x6 1 x8 x6 1 x d a e r10 10 a - 6 a0 a - 5 a0 a n a s s e r d d a d a e r e s a r e11 10 a - 6 a0 a - 5 a0 a n a s s e r d d a r a e l c e t i r w11 00 a - 6 a0 a - 5 a0 d - 7 d0 d - 5 1 d0 a n a s s e r d d a e t i r w n e w e10 0 x x x x x 1 1x x x x 1 1 e l b a n e e t i r w s d w e10 0 x x x x x 0 0x x x x 0 0 e l b a s i d e t i r w l a r e10 0 x x x x x 0 1x x x x 0 1 s e s s e r d d a l l a r a e l c l a r w10 0 x x x x x 1 0x x x x 1 0 0 d - 7 d0 d - 5 1 ds e s s e r d d a l l a e t i r w
cat93c46r 5 doc no. 1107, rev. f ?2006 by catalyst semiconductor, inc. characteristics subject to change without notice figure 1. sychronous data timing figure 2. read instruction timing sk di cs do t dis t pd0, t pd1 t csmin t css t dis t dih t skhi t csh valid valid data valid t sklow sk cs di do t csmin standby t hz high-z high-z 11 0 a n a n 1 a 0 0 d n d n 1 d 1 d 0 t pd0 figure 2b. sequential read instruction timing sk cs di do high-z 11 0 a n a n 1 a 0 dummy 0 d 15 . . . d 0 or d 7 . . . d 0 1 11 1 111 11111111 address + 1 d 15 . . . d 0 or d 7 . . . d 0 address + 2 d 15 . . . d 0 or d 7 . . . d 0 address + n d 15 . . . or d 7 . . . don't care figure 3. ewen/ewds instruction timing sk cs di standby 10 0 * * enable=11 disable=00
cat93c46r 6 doc. no. 1107, rev. f ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice sk cs di do t cs min standby high-z high-z 101 a n a n-1 a 0 d n d 0 busy ready status verify t sv t hz t ew figure 4. write instruction timing write after receiving a write command, address and the data, the cs (chip select) pin must be deselected for a minimum of t csmin (see design note for details). the falling edge of cs will start the self clocking clear and data store cycle of the memory location specified in the instruction. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c46r can be determined by selecting the device and polling the do pin. since this device features auto-clear before write, it is not necessary to erase a memory location before it is written into. erase upon receiving an erase command and address, the cs (chip select) pin must be deasserted for a minimum of t csmin after the proper number of clock pulses (see design note ). the falling edge of cs will start the self clocking clear cycle of the selected memory location. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/ busy status of the cat93c46r can be determined by selecting the device and polling the do pin. once cleared, the content of a cleared location returns to a logical 1 state. erase all upon receiving an eral command, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking clear cycle of all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c46r can be determined by selecting the device and polling the do pin. once cleared, the contents of all memory bits return to a logical 1 state. write all upon receiving a wral command and data, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking data write to all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. (note 1.) the ready/ busy status of the cat93c46r can be determined by selecting the device and polling the do pin. it is not necessary for all memory locations to be cleared before the wral command is executed. design note with cat93c46r, after the last data bit has been sampled, chip select (cs) must be brought low before the next rising edge of the clock(sk) in order to start the slef-timed high voltage cycle. this is important because if the cs is brought low before or after this specific frame window, the addressed location will not be programmed or erased.
cat93c46r 7 doc no. 1107, rev. f ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice figure 5. erase instruction timing sk cs di do standby high-z high-z 1 a n a n-1 busy ready status verify t sv t hz t ew t cs min 11 a 0 figure 7. wral instruction timing figure 6. eral instruction timing sk cs di do standby t cs min high-z high-z 10 1 busy ready status verify t sv t hz t ew 00 status verify sk cs di do standby high-z 10 1 busy ready t sv t hz t ew t cs min d n d 0 0 0
cat93c46r 8 doc. no. 1107, rev. f ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice 8-lead 300 mil wide plastic dip (l) a e b e1 b2 l a2 a1 e d eb 24c16_8-lead_dip_(300p).eps symbol a a1 b b2 d e e1 e eb l min 0.38 0.36 9.02 7.62 6.09 6.35 7.87 0.115 0.130 0.150 nom 0.46 1.77 1.14 7.87 2.54 bsc max 4.57 a2 3.05 3.81 0.56 10.16 8.25 7.11 9.65 notes: 1. all dimensions are in millimeters. 2. complies with jedec standard ms001. 3. dimensioning and tolerancing per ansi y14.5m-1982
cat93c46r 9 doc no. 1107, rev. f ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice 8-lead 150 mil wide soic (v, w) 24c16_8-lead_soic.eps symbol a1 a b c d e e1 h l min 0.10 1.35 0.33 4.80 5.80 3.80 0.25 0.40 nom 0.25 0.19 max 0.25 1.75 0.51 5.00 6.20 4.00 e 1.27 bsc 0.50 1.27 10 8 e e1 d a1 e l 1 c b h x 45 a notes: 1. all dimensions are in millimeters. 2. complies with jedec specification ms-012. for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf.
cat93c46r 10 doc. no. 1107, rev. f ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice 8-lead tssop (y) 8 5 1 4 e e1 e/2 pin #1 ident. d b l 1 e a a1 a2 see detail a see detail a seating plane c gage plane 0.25 symbol a a1 a2 b c d e e1 e l 1 min 0.05 0.80 0.09 2.90 6.30 6.4 4.30 0.00 8.00 nom 0.90 0.30 0.19 3.00 4.40 0.60 0.75 0.50 max 1.20 0.15 1.05 0.20 3.10 6.50 4.50 0.65 bsc notes: 1. all dimensions are in millimeters. 2. complies with jedec standard mo-153 for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf.
cat93c46r 11 doc no. 1107, rev. f ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice e2 a2 e pin 1 index area l tdfn2x3 ( 03 ) .e ps a3 pin 1 id e b a1 3 x e d2 d a symbol a a1 a2 a3 b d d2 e e2 e l min 0.70 0.00 0.45 0.20 1.90 1.30 1.40 2.90 1.20 0.20 0.30 0.40 nom 0.75 0.02 0.55 0.20 ref 0.25 2.00 3.00 0.50 typ max 0.80 0.05 0.65 0.30 2.10 1.50 3.10 1.40 1.30 notes: 1. all dimensions are in millimeters. 2. complies with jedec specification ms-229. for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf. 8-pad tdfn 2x3 package (vp2)
cat93c46r 12 doc. no. 1107, rev. f ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice ordering information prefix device # suffix 93c46r v i product number 93c46r cat temperature range i = industrial (-40 c - 85 c) optional company id package l = pdip v = soic, jedec w = soic, jedec x = soic, eiaj (4) y = tssop vp2 = tdfn (2x3mm) tape & reel t: tape & reel 2: 2000/reel (4) 3: 3000/reel lead finish g: nipdau t3 ? g notes: (1) all packages are rohs-compliant (lead-free, halogen-free). (2) the standard lead finish is nipdau. (3) the device used in the above example is a cat93c46rvi-gt3 (soic, industrial temperature, nipdau, tape & reel). (4) for soic, eiaj (x) package the standard lead finish is matte-tin. this package is available in 2000 pcs/reel, i.e. cat93c46r xi-t2. (5) for additional package and temperature options, please contact your nearest catalyst semiconductor sales office.
copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 minipot quad-mode catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability arising out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semiconductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale. catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. publication #: 1107 revison: f issue date: 09/11/06 revision history e t a dn o i s i v e rs t n e m m o c 5 0 / 1 0 / 2 1a e u s s i l a i t i n i 5 0 / 7 0 / 2 1b s c i t s i r e t c a r a h c g n i t a r e p o . c . d e t a d p u 5 0 / 4 1 / 2 1c s n o i t c n u f n i p e t a d p u n o i t a m r o f n i g n i r e d r o e t a d p u 6 0 / 6 0 / 3 0d s e r u t a e f e t a d p u n o i t a r u g i f n o c n i p e t a d p u s c i t s i r e t c a r a h c . c . a e t a d p u n o i t a r e p o e c i v e d e t a d p u s n o i s n e m i d e g a k c a p e t a d p u g n i k r a m e g a k c a p e t a d p u l e e r d n a e p a t e t a d p u 6 0 / 6 1 / 5 0e n o i t a r u g i f n o c n i p e t a d p u s c i t s i r e t c a r a h c g n i t a r e p o . c . d e t a d p u s c i t s i r e t c a r a h c . c . a e t a d p u n o i t a r e p o e c i v e d e t a d p u g n i k r a m e g a k c a p e t a d p u l e e r d n a e p a t e t a d p u 6 0 / 1 1 / 9 0f s e r u t a e f e t a d p u n o i t p i r c s e d e t a d p u s n o i t c n u f n i p e t a d p u l o b m y s l a n o i t c n u f e t a d p u s g n i t a r m u m i x a m e t u l o s b a e t a d p u s c i t s i r e t c a r a h c y t i l i b a i l e r e t a d p u s c i t s i r e t c a r a h c g n i t a r e p o . c . d e t d a p u e c n a t i c a p a c n i p e t a d p u s c i t s i r e t c a r a h c . c . a e t a d p u s m a r g a i d g n i m i t e t a d p u s n o i s n e m i d e g a k c a p e t a d p u g n i k r a m e g a k c a p e v o m e r n o i t a m r o f n i g n i r e d r o e t a d p u catalyst semiconductor, inc. corporate headquarters 2975 stender way santa clara, ca 95054 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com

▲Up To Search▲

Price & Availability of CAT93C46RYI-G3

	To Download CAT93C46RYI-G3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .